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TECH

 

 

Integrated Circuit Roadmap

 

Senseeker has an established heritage in delivering state-of-the-art readout IC designs including the industry's smallest dual-band (6 µm pitch) readout IC, multi-modal digital readout ICs (DROICs) and high dynamic range digital pixel readouts (DPROICs). New R&D activity is focused on DPROIC innovation and advanced transducer SoCs that combine sensors and drivers to optimize functionality and SWaP.

 

 

 

 

 

Research & Development

 

Senseeker Engineering is proud to have participated in several U.S. Government funded Small Business Innovation Research (SBIR) projects that have stimulated technical innovation in support of federal research and development needs. Selected SBIR Phase II efforts are summarized below.

 

 

Digital Pixel Readout Integrated Circuit for High Dynamic Range Infrared Imaging Applications

NASA SBIR Phase II | Awarded 2019

 

This proposal outlines a digital pixel readout integrated circuit (DPROIC) to achieve extremely high dynamic range, high speed and elegant functionality for infrared image focal plane arrays. This digital pixel readout will be a complete camera-on-chip architecture when combined with single or dual polarity dual band detectors in a hybrid fashion. It will have a wide operating temperature range to support a broad range of detector architectures.   read more 

 

 

 

Digital Pixel Sensor with Efficient On-Chip Data Compression

Army SBIR Phase II | Awarded 2018

 

This proposal outlines a very high dynamic range large-format small-pitch low-power digital pixel readout integrated circuit (DPROIC) for infrared focal plane arrays and will be designed to support an entire family of formats.This DPROIC will have on-chip compression for efficient transmission of data on large format, fast data rate sensors.   read more 

 

 

 

Smart Readout Integrated Circuit for Dual Band Infrared Focal Plane Arrays

MDA SBIR Phase II | Awarded 2017

 

This proposal outlines a large-format small-pitch low-power digital pixel readout integrated circuit (DPROIC) for dual-band infrared focal plane arrays to achieve high sensitivity, high resolution, large dynamic range, low noise, large field of view and fast data rate. This digital pixel readout will be a complete camera-on-chip architecture when combined with single or dual polarity dual band detectors in a hybrid fashion.   read more 

 

 

 

High Speed High Dynamic Range Digital Pixel Sensor

Army SBIR Phase II | Awarded 2015

 

Senseeker Engineering Inc. is designing a digital pixel ROIC to support a wide variety of detector types across a broad swath of applications such as brown-out reduction, biometrics, hazard monitoring, surveillance, and industrial robotics. Such systems require a pixel architecture capable of delivering high dynamic range and high sensitivity to process a wide range of flux levels, especially when coupled to LWIR detectors.   read more 

 

 

 

 

 

White Papers

 

Digital Readout Integrated Circuit for High Dynamic Range Infrared Imaging

 

A 1280 x 720 format, 8 µm pixel pitch digital readout integrated circuit (DROIC) for intra-frame high dynamic range (HDR) infrared imaging is presented. Unlike traditional inter-frame HDR imaging where frames with different integration times are temporally combined to obtain an HDR frame, intra-frame HDR imaging is accomplished by spatially interpolating neighboring pixels with different integration times to obtain HDR pixels, thereby achieving the same level of dynamic range improvement without compromising temporal resolution and mostly retaining spatial resolution. In intraframe HDR mode, the infrared imager can achieve a phenomenal >57 dB improvement in dynamic range over normal mode.

 

 

 

Proximal Interpolation, Tone Mapping and Pseudo-Coloring for Intra-Frame High Dynamic Range Infrared Imaging

 

Intra-frame high dynamic range (HDR) infrared imaging is accomplished in a 1280 x 720 format, 8 μm pixel pitch digital readout integrated circuit (DROIC) by spatially combining neighboring pixels with different integration times to obtain HDR pixels. Intra-frame HDR imaging achieves the same level of dynamic range improvement as traditional inter-frame HDR imaging without compromising temporal resolution. Proximal interpolation to retain the spatial resolution of the HDR infrared frame, tone mapping to effectively display HDR infrared content on limited dynamic range displays, and pseudo-coloring to better visualize HDR infrared imagery are discussed.

 

 

 

 

 

 

Patents

 

Charge transfer circuit for compact modulators

US Patent No. US 11,005,495 | Granted May 11, 2021

 

The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.

 

Dynamic resistance element analog counter

US Patent No. US 10,594,299 | Granted March 17, 2020

 

The present disclosure provides an analog counter circuit for use in a minimal-sized circuitry. The analog counter circuit of the present disclosure can provide much higher resolution versus power consumption and layout area as compared to conventional digital counters. The analog counter circuit of the present disclosure can also provide much better bias supply management, step accuracy, multi-element step uniformity and lower supply spiking as compared to conventional analog counter architectures. The compact size of the disclosed counter circuit allows better integration of arrayed elements, such as, an array of image sensing pixels or an array of artificial neurons.   read more 

 

Electronic Circuit having Dynamic Resistance Element

US Patent No. US 10,136,083 | Granted November 20, 2018

 

The present disclosure provides a delta-sigma modulator circuit for use in a pixelated image sensor or a readout integrated circuit. In one aspect, the modulator circuit includes a dynamic resistance element configured to have a variable resistance that changes in accordance with a voltage difference across the dynamic resistance element.   read more 

 

Calibration for a Single Ramp Multi Slope Analog-To-Digital Converter

US Patent No. US 9,337,856 | Granted May 10, 2016

 

Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge and discharge elements of different time constant i.e. slope, wherein the relationships between slopes is defined as a function of the shallowest slope SN such that S1=K1·SN, S2=K2·SN, . . . SN-1=KN-1·SN-1 where the K values are integers, and the code count for conversion is C=K1·C1+K2·C2+ . . . KN-1·CN-1+CN where each Ci represents an observed counts per each slope for a conversion, including; sampling for a first calibration pass a voltage with the ADC, discharging the voltage on the steepest slope for a number of counter counts C11, charging and discharging on the remaining slopes up to K2 to KN-1 for a number of counts per slope, Ci1 e.g. C21 to CN-1,1, discharging the remaining voltage residue on the shallowest slope and note the count, CN,1, sampling the same voltage on the ADC for a second calibration pass, discharging the voltage on the steepest slope for a modified number of counter counts C12=C11+/−X, modifying the number of charge/discharge counts time Ci2 for the slopes K2 to KN-1 to adjust for the change expected from the modified steep slope discharge to reach the shallowest slope with the same expected residue as for the first calibration pass, discharging the remaining voltage residue on the shallowest slope and note the actual count, CN,2, adjusting K1 to K1a based on the difference between CN,1 and CN,2, and; using C=K1a·C1+K2·C2+ . . . KN-1·CN-1+CN as the count code for conversion.   read more 

 

Wide Bias Background Subtraction Pixel Front-End with Short Protection

US Patent No. US 8,981,437 | Granted March 17, 2015

 

Pixel Front end circuits particularly applicable to photodetectors requiring wide bias ranges and/or with high background currents. In various versions, wide bias ranges, short protection, and background current subtraction, both predetermined and automatically sampled, are disclosed.   read more 

 

 

 

 

Publications

 

Proximal Interpolation, Tone Mapping and Pseudo-Coloring for Intra-Frame High Dynamic Range Infrared Imaging

T. Poonnen, W. Korth, C. Peterson, and K. Veeder | Proceedings of SPIE Defense + Commercial Sensing Conference, 2022

 

Intra-frame high dynamic range (HDR) infrared imaging is accomplished in a 1280 x 720 format, 8 µm pixel pitch digital readout integrated circuit (DROIC) by spatially combining neighboring pixels with different integration times to obtain HDR pixels. Intra-frame HDR imaging achieves the same level of dynamic range improvement as traditional inter-frame HDR imaging without compromising temporal resolution. Proximal interpolation to retain the spatial resolution of the HDR infrared frame, tone mapping to effectively display HDR infrared content on limited dynamic range displays, and pseudo-coloring to better visualize HDR infrared imagery are discussed.   read more 

 

Digital Readout Integrated Circuit for High Dynamic Range Infrared Imaging

T. Poonnen, S. McCotter, K. Esparza, and K. Veeder | Proceedings of SPIE Defense + Commercial Sensing Conference, 2021

 

A 1280 x 720 format, 8 μm pixel pitch digital readout integrated circuit (DROIC) for intra-frame high dynamic range (HDR) infrared imaging is presented. Unlike traditional inter-frame HDR imaging where frames with different integration times are temporally combined to obtain an HDR frame, intra-frame HDR imaging is accomplished by spatially interpolating neighboring pixels with different integration times to obtain HDR pixels, thereby achieving the same level of dynamic range improvement without compromising temporal resolution and mostly retaining spatial resolution. In intraframe HDR mode, the infrared imager can achieve a phenomenal >57 dB improvement in dynamic range over normal mode.   read more 

 

Digital Converters for Image Sensors

K. Veeder | SPIE Press Book, ISBN: 9781628413892, 2015

 

This book is intended for image sensor professionals and those interested in the boundary between sensor systems and analog and mixed-signal integrated circuit design. It provides in-depth tips and techniques necessary to understand and implement these two types of complex circuit systems together for a wide variety of architectures or trade off one against another. The tutorial begins with a brief introduction to the history and definition of a digital image sensor, as well as converter characteristics, before addressing DAC and ADC architectures. Later chapters cover pipeline ADC designs, digital correction, calibration, and testing according to IEEE standards.   read more 

 

Fundamentals of Infrared and Visible Detector Operation and Testing

J. D. Vincent, S. E. Hodges, J. Vampola, M. Stegall, and G. Pierce | Wiley, ISBN: 9781119011897, 2015

 

This book discusses how to use and test infrared and visible detectors. The book provides a convenient reference for those entering the field of IR detector design, test or use; those who work in the peripheral areas; and those who teach and train others in the field.   read more 

 

 

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